Metal oxide semi-conductor (MOS) circuits, and particularly MOS integrated circuits are vulnerable to damage through electrostatic discharge (ESD). Damage results primarily from two mechanisms: charge injection and thermal degradation. Damage may manifest itself as failed circuits, margin shifts, or latent defects that continue to degrade, contributing to premature product failure. Eliminating ESD related defects requires on-chip protection structures as well as assembly and handling precaution measures. On-chip protection structures are often called input protection device (IPD) circuits, for example, input protection diodes are a type of prior art IPD circuit. Assembly and handling measures include transporting integrated circuits in conductive foam, conductive wrist straps for operators handling devices, and ionized air environments, as well as other measures.
There are three principle sources of charge that can result in damaging ESD events. The first source is human body discharge (HBD), wherein a charged person touches a device and discharges through the device to a ground, usually destroying the device. The second source is the device itself being charged and a discharge occurring when the device comes near a ground circuit. This type of discharge is faster and more severe than human body discharge. The third source is field induced charge wherein an external field induces a damaging or charging potential exceeding dielectric breakdown or creating trapped inversion charge.
Electrostatic voltage generation can result from triboelectric charging, caused by rapid separation of two materials--including gases or liquids flowing across a surface--which creates equal and opposite charges. Capacitive and inductive charging can also occur. Even in high humidity environments, voltages are still significant. Elevated humidity can reduce voltages below perceptible levels (approximately 3 KV) but not below damage thresholds, which can be as low as 30 volts.
The conventional approach to protecting MOS devices for ESD or electrical overstress voltages is to place p/n junction devices such as diodes and transistors in parallel with the input gate, such as illustrated in "Gate Protection for CMOS/SOS", R. Pancholy, in Proceedings of the 15th IEEE International Rel. Physics Symposium, pp. 132-137, 1977. This article also illustrates arc gap, also called spark gap, structures.
The ideal characteristics of an IPD network include limiting fast and slow rise time overvoltage events to below the dielectric breakdown voltage of the gate without degrading timing or logic operation. In today's electronics industry, ESD damage thresholds greater than 2000 volts are desired. High performance circuits require pad and IPD network designs that introduce negligible parasitic components, respond to the overvoltage transient faster than the damage mechanism of the gate dielectric, and require a minimum of layout area. Further, fabrication of the IPD network must be compatible with the integrated circuit fabrication technology being used, and the network must be stable in accelerated voltage/temperature quality screen environments, in radiation environments, and stable under repeated ESD/electrical overstress voltage events.
As referenced above, arc gap structures of planar parallel and saw-tooth geometry have been used in conjunction with p/n junction devices for input protection. These structures are not effective IPDs for high performance circuits because they rely on ionization discharge.
Ionization discharge requires a high electric field to strip electrons off atoms and molecules to form a conductive ionized plasma discharge path between cathode and anode conductors. The electric field must exceed the ionization potential of the intervening medium, and the spacing required to create the field is limited to dimensions determined by the photolithographic and design rule restrictions of the process. If the electric field is high enough, and the spacing small enough, a plasma is formed and electron discharge from the cathode occurs.
An arc event is usually destructive to the cathode and anode because of sputtering by ions in the plasma of the cathode, and vaporization of ions from both cathode and anode. Further, the process is relatively slow compared to the charge injection/trapping/breakdown mechanism of the thin gate dielectric. For this reason, arc gap IPDs use a series resistor and a parallel diode to slow the ESD rise time and provide a parallel path for current.
High performance circuits cannot tolerate the series resistance required for arc gap operation, and parasitic capacitance associated with p/n junction devices and their interconnection limits performance. Indeed, many high speed ICs make significant tradeoffs between pad performance and ESD protection, settling for less than 300 volt damage threshold with human body discharge to achieve timing and performance requirements.
Electrostatic discharge problems have plagued the electronics industry since MOS devices have been in use, with unprotected damage thresholds measured in the tens of volts, but handling and application requirements demanding protection to several thousand volts. There is need in the art then for a new type of input protection device to discharge high voltage from an input pad of an integrated circuit. There is a further need for such a device that provides improved response time, negligible parasitics, and high damage thresholds. There is a further need for such a device that can respond effectively to all three discharge sources.